module top ;
wire a,b ;
reg c ;
system_clock #100 clock1 (a) ;
system_clock #50 clock1 (b) ;
always#1 c=a & b ;//延遲1個時間單位//
endmodule
module system_clock (CLK) ;
parameter PERIOD = 100 ;
output CLK ;
reg CLK ;
initialCLK=0 ;
always
begin
#(PERIOD/2) CLK=~CLK ;
#(PERIOD/2) CLK=~CLK ;
endalways @ (posedge CLK)if ($time>1000)
#(PERIOD-1)$stop
endmodule
