12月29日加分考

11月11日2位元比較器

module top;
wire a,b,c,d;
wire e,f,g;
sclock #200 clock(a);
sclock #100 clock(b);
sclock #50 clock(c);
sclock #25 clock(d);
xxx t(e,f,g,a,b,c,d);
endmodule

module xxx(e,f,g,a,b,c,d);
input a,b,c,d;
ouput e,f,g;
wire w1,w2,w3,w4,w5,w6,w7;
or(e,w1,w2,w3);
nor(f,e,g);
and(g,w4,w5);
and(w1,w6,d);
and(w2,w6,w7.c);
and(w3,w7,c,d);
not(w6,b);
not(w7,a);
xnor(w4,b,d);
xnor(w5,a,c);
endmodule

module sclock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2) clk=~clk;
#(PERIOD/2) clk=~clk;
endalways@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

10月20日上課內容(AOI_4_UNIT)

module AOI_4_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
reg y_out,y1,y2;
//wire y1,y2;
always
begin
#1 y1=x_in1 & x_in2;
#1 y2=x_in3 & x_in4;
#1 y_out=~(y1 y2);
/*and#1 (y1,x_in1,x_in2);
and #1 (y2,x_in3,x_in4);
nor #1 (y_out,y1,y2);
*/
end
endmodule
module textbench;
reg x_in1,x_in2,x_in3,x_in4;
wire y_out;
AOI_4_Unit A1(y_out,x_in1,x_in2,x_in3,x_in4);
initial
begin
x_in1=0;x_in2=0;x_in3=0;x_in4=0;
#10 x_in1=0;x_in2=1;x_in3=0;x_in4=1;
#10 x_in1=1;x_in2=0;x_in3=1;x_in4=0;
#10 x_in1=1;x_in2=1;x_in3=1;x_in4=1;
#10 $finish;
end
endmodule

10月13第二次上課內容

module top;
wire a,b;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
Add_half AH1(sum,c_out,a,b);
endmodule
module Add_half(sum,c_out, a, b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule
module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;initialclk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

10月6日第一次實作

補上兩張10月06日的圖

10月6日第一次實作(文)

module top ;
wire a,b ;
reg c ;
system_clock #100 clock1 (a) ;
system_clock #50 clock1 (b) ;
always#1 c=a & b ;//延遲1個時間單位//
endmodule
module system_clock (CLK) ;
parameter PERIOD = 100 ;
output CLK ;
reg CLK ;
initialCLK=0 ;
always
begin
#(PERIOD/2) CLK=~CLK ;
#(PERIOD/2) CLK=~CLK ;
endalways @ (posedge CLK)if ($time>1000)
#(PERIOD-1)$stop
endmodule