10月20日上課內容(AOI_4_UNIT)

module AOI_4_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
reg y_out,y1,y2;
//wire y1,y2;
always
begin
#1 y1=x_in1 & x_in2;
#1 y2=x_in3 & x_in4;
#1 y_out=~(y1 y2);
/*and#1 (y1,x_in1,x_in2);
and #1 (y2,x_in3,x_in4);
nor #1 (y_out,y1,y2);
*/
end
endmodule
module textbench;
reg x_in1,x_in2,x_in3,x_in4;
wire y_out;
AOI_4_Unit A1(y_out,x_in1,x_in2,x_in3,x_in4);
initial
begin
x_in1=0;x_in2=0;x_in3=0;x_in4=0;
#10 x_in1=0;x_in2=1;x_in3=0;x_in4=1;
#10 x_in1=1;x_in2=0;x_in3=1;x_in4=0;
#10 x_in1=1;x_in2=1;x_in3=1;x_in4=1;
#10 $finish;
end
endmodule